1. Field of the Invention
This invention relates to a method of improving performance of a multichip cube structure, and more particularly, to a method of using foamed insulators to reduce the capacitive load of circuitry in the cube structure.
2. Description of the Related Art
To provide improved performance, manufacturers of integrated circuit devices continually strive to increase circuit density. Such devices are typically formed on a semiconductor substrate, such as a silicon wafer, and comprise a large number of miniaturized circuit elements. These elements, which include transistors, diodes, capacitors, and resistors, are usually disposed within or adjacent the substrate and define a plurality of circuit nodes. To combine the circuit elements into a useful electronic circuit, integrated circuit devices require a plurality of conducting paths that link the circuit nodes in a preferred manner. Typically, the conducting paths are provided by electrical interconnects comprising wires of aluminum or aluminum alloy that are embedded in a layer of insulating SiO2.
However, as circuit density is increased, problems associated with conventional electrical interconnects are becoming more apparent. In particular, a higher density device having an increased number of circuit elements will likely require an even greater increase in the number of electrical interconnects. Consequently, the electrical interconnects will need to have a reduced thickness and adjacent interconnects will need to be spaced more closely together. Unfortunately, such dimensional reductions tend to increase the resistance of individual interconnects and increase the capacitance between adjacent interconnects, thereby possibly increasing signal propagation delays and signal cross-talk.
This problem is particularly apparent in high density electronic packaging modules such as multichip cube structures or three-dimensional multi-chip structures. A multichip cube structure typically comprises a plurality of semiconductor chips that are adhered together in a stack. It is generally understood that each chip in the stack has conductive leads that extend to one edge of the chip so as to provide electrical contact with external circuitry. In most multichip cube structures, the conductive leads on the chips are closely spaced where adjacent leads are sometimes separated by less than 1 micron. Shrinking the distance between adjacent leads can adversely increase the capacitive load. Furthermore, stacking the chips in close proximity to one another as required in multichip cube structures can also increase the capacitive coupling between electrical interconnects on adjacent chips.
To address the problem of increased capacitive coupling between adjacent interconnects, designers have tried substituting materials having lower dielectric constants for the more commonly used oxide insulators such as SiO2. In some cases, polymers such as polyimides have been used in place of SiO2, however polyimides provide only limited improvement as the dielectric constant of polyimide (2.8-3.5) is only slightly lower than that of conventional oxide insulators. Furthermore, interconnects comprising an air bridge have also been developed as described in U.S. Pat. No. 5,891,797. The air bridge is a length of conducting material that extends from a first supported end to a second supported end through an air space such that the bridge is substantially surrounded by air. Consequently, because air has a dielectric constant that is substantially less than that of SiO2, the capacitance between adjacent interconnects is reduced. However, the use of air-bridged structures will pose some additional problems in packaging as it does not protect the metal interconnect structure from environmental attacks. They will also prove difficult to assemble in very dense packaging schemes such as multichip cube structures.
Hence from the foregoing, it will be appreciated that there is a need for a method to reduce the capacitive load of electrical interconnects in multichip cube structures. To this end, there is a particular need for a low dielectric insulating material that can isolate adjacent chips in a multichip cube structure and decrease the capacitive load of the interconnects in adjacent chips. Furthermore, there is also a need for the insulating material to retain the desirable physical and mechanical properties afforded by the conventional insulating materials used in multichip cube structure.
The aforementioned needs are satisfied by the device and process of the present invention which is directed to the manufacture of a high density semiconductor structure having reduced capacitive coupling between electrical interconnects. In one aspect, the high density semiconductor structure comprises a first integrated circuit chip having an upper bonding surface and a second integrated circuit chip secured to the first chip in a manner such that a lower bonding surface of the second chip is positioned adjacent to the upper bonding surface of the first chip. The semiconductor structure also includes a chip insulating layer that is interposed between the first and second chips so as to provide electrical isolation between the chips. Furthermore, the insulating layer comprises an insulating material and a plurality of enclosed regions of air dispersed throughout the insulating material. Preferably, the enclosed regions of air cause the dielectric constant of the insulating layer to be less than the dielectric constant of the insulating material.
In another embodiment, the semiconductor structure further comprises a conductor insulating layer formed on the upper bonding surface of the first chip so as to provide electrical isolation between adjacent conductive leads disposed on the upper surface thereof. Furthermore, the conductor insulating layer comprises an insulating material and a plurality of enclosed regions of air dispersed throughout the insulating material. Preferably, the enclosed regions of air cause the dielectric constant of the insulating layer to be lower than the dielectric constant of the insulating material.
In yet another embodiment, the semiconductor structure further comprises a third integrated circuit chip that is secured to the second chip in a manner such that a lower bonding surface of the third chip is positioned adjacent to an upper bonding surface of the second chip. Preferably, an insulating layer is also disposed between the second and third chips. The insulating layer may comprises a foamed polyimide material. In one embodiment, an additional insulating layer may also be formed on a lower surface of the first chip so as to insulate the exposed back surface of the chip. Preferably, the insulating layer also comprises a foamed polymeric material.
In another aspect, the present invention provides a multichip cube structure comprising a first integrated circuit chip having a first insulating layer disposed on an upper surface of the chip so as to electrically isolate a plurality of electrical interconnects disposed on the upper surface thereof. Furthermore, the first insulating layer is comprised of an insulating material having a first dielectric constant. Preferably, at least a portion of the first insulating layer contains enclosed regions of air that reduce the dielectric constant of the first insulating layer to a value lower than the first dielectric constant.
The multichip cube structure also includes a second integrated circuit chip secured to the first chip in a manner such that a lower surface of the second chip is positioned adjacent the upper surface of the first chip. Furthermore, a second insulating layer is interposed between the first and second chips. Preferably, the second insulating layer is comprised of a second insulating material having a second dielectric constant and at least a portion of the second insulating layer contains a plurality of enclosed regions of air that reduce the dielectric constant of the second insulating layer to a value lower than the second dielectric constant.
In yet another aspect, the present invention provides a method of manufacturing a multichip cube structure having reduced capacitive loading in the electrical interconnects. The method comprises forming an insulating layer on an upper bonding surface of a first chip; reducing the dielectric constant of the insulating layer by creating a plurality of voids in the insulating layer; and securing a second chip to the upper bonding surface of the first chip wherein a lower bonding surface of the second chip is positioned adjacent the upper surface of the insulating layer on the first chip. The voids in the insulating layer reduce the dielectric constant of the insulating layer, thereby permitting the chips to be stacked closer together without significantly increasing the capacitive load of the interconnects.
Advantageously, the present invention provides a high density semiconductor device having an insulating material with a dielectric constant that is lower than that of most known insulating materials. It is generally understood that the dielectric constant of the insulating material directly affects the capacitive load of the circuits and that a lower dielectric constant will decrease the capacitive coupling of electrical interconnects between adjacent chips in the device. Furthermore, the insulating material of the present invention not only provides a lower dielectric constant but also retains the favorable physical and mechanical properties of most conventional polymeric materials. As such, the present invention provides densely packaged multichip cube structures with a novel insulating material that provides effective electrical isolation between closely spaced adjacent chips and does not reduce the speed of signal propagation through the electrical interconnections. These and other advantages of the present invention will become more fully apparent from the following description taken in conjunction with the accompanying drawings.